(1) Field of the Invention
The invention relates to the fabrication of integrated, circuit devices, and more particularly, to a method and apparatus of marking defective contacts by electroplating and by observing the electroplated contacts.
(2) Description of the Prior Art
For the mass production of semiconductor devices silicon, in single or in polycrystalline form, is most widely used. Repetitive patterns of identical circuits or circuit elements are patterned on a single silicon wafer. A large variety of materials is thereby used to create the semiconductor devices, these material can be electrically conductive, electrically non-conductive (isolating) or electrically semi-conductive. A common technique to control the conductivity of various regions in a semiconductor device is the addition of impurities or dopants. Dopants can be of one of two types: dopants which have one less valence electron than the doped material, normally silicon, and therefore introduce P-type impurities, and dopants that have one more valence electron than the doped material and therefore introduce N-type impurities in the doped material. An example of P-type dopant is boron; an example of N-type dopant is phosphorous. Silicon doped with boron therefore becomes P-type silicon while silicon doped with phosphorous becomes N-type silicon.
Areas to which electrical contacts must be made are normally referred to as active areas. Examples of active areas to which electrical contacts must be established are the source and drain regions of DRAM devices; these source and drain regions are created as specially doped regions in the surface of the semiconductor substrate. Methods of establishing electrical contact between layers of conductive metal or interconnecting wiring use via holes between the various layers to create electrical contact from one level to adjacent levels. Continued miniaturization of semiconductor devices has led to continued emphasis on reliability and yield aspects that are encountered in the creation of via holes. Via holes may be created in layers of dielectric or insulator and may have a diameter smaller than 0.5 um. Filling of these vias presents special problems of even and uniform flow rate of the metal that is used to fill the vias in addition to problems of surface planarity and the appearance of surface irregularities in the surface of the vias after planarization. Other problems relate to adherence of the deposited metal to the created via opening, uniformity of profile of the created via, aspect ratio of the created hole and problems created by holes with high aspect ratios. It is, for instance, difficult to deposit aluminum using Chemical Vapor Deposition techniques and to obtain a deposition in the filled opening that is uniform. The sputtering of aluminum frequently leads to uneven deposition inside the via hole where this hole has micron or sub-micron dimensions. Uneven distribution of the sputtered aluminum results in. Uneven current densities that can cause electromigration and problems of via reliability. The recent trend has therefore been to use tungsten filler for contact openings where this tungsten is deposited using Low Pressure CVD (LPCVD) techniques. Tungsten is characterized by a more even distribution of the tungsten inside the hole after depositing and is therefore less prone to electromigration and problems of via reliability.
For the creation of contact vias, the Damascene process is used for a number of applications. The most commonly applied process is first metal or local interconnects. Some early Damascene structures have been achieved using Reactive Ion Etching (RIE) but Chemical Mechanical Planarization (CMP) is used exclusively today. Metal interconnects using Damascene of copper and of aluminum are also being explored. The Damascene process first forms a metal plug in the surface of the substrate after which an intra-level dielectric (ILD, for instance SiO2) is deposited using for instance Plasma Enhanced CVD (PECVD) technology. Trenches are created in the ILD for metal lines using Reactive Ion Etching (RIE) technology, a layer of metal is deposited over the trenches (using either CVD or a metal flow process) and planarized down to the top surface of the ILD using the CMP process. The metal plug is aligned with some of the metal lines and forms a first level interconnect.
The application of the Damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the Damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale integrated devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices. Even for these applications however, the wolfram plug is still used for contact points in order to avoid damage to the devices.
An extension of the damascene process is the dual damascene process whereby an insulating or dielectric material, such as silicon oxide, is patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. One of the dual damascene approaches uses a dielectric layer that is formed by three consecutive depositions whereby the central layer functions as an etch stop layer. This etch stop layer can be SiN, the top and bottom layer of this three layer configuration can be SiO2. This triple layer dielectric allows first forming the vias by resist patterning the vias and etching through the three layers of dielectric. The conductive pattern can then be formed in the top layer of dielectric whereby the central layer of SiN forms the stop layer for the etch of the conducting pattern. Another approach, still using the three-layer dielectric formed on the substrate surface, is to first form the pattern for the conducting lines in the top layer of the dielectric whereby the SiN layer again serves as etch stop. The vias can then be formed by aligning the via pattern with the pattern of the conducting lines and patterning and etching the vias through the etch stop layer of SiN and the first layer of dielectric. Yet another approach is to deposit the three layer dielectric in two steps, first depositing the first layer of SiO2 and the etch stop layer of SiN. At this point the via pattern can be exposed and etched. The top layer of SiO2 dielectric is then deposited; the conducting lines are now patterned and etched. The SiN layer will stop the etching except where the via openings have already been etched.
Yet another approach to forming the dual damascene structure is to form an insulating layer that is coated with a photoresist. The photoresist is exposed through a first mask with image pattern of the via openings, this via pattern is anisotropically etched in the upper half of the insulating layer. The photoresist now is exposed through a second mask with an image pattern of the conductive line. The pattern of the conducting lines is aligned with the pattern of the vias thereby encompassing the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
For all of the above-indicated examples it is required that a dependable method is available to perform contact hole analysis. This analysis can be a direct analysis of contact holes or it can be an analysis of contact holes that is initiated by chip testing results that raise questions of contact hole performance. In these cases it is important that abnormal contact holes can be readily and dependably located for further analysis.
U.S. Pat. No. 3,719,884 (Laroche) shows a method and apparatus to find pinholes by electroplating a component (varnish) and measuring the current consumed. The prior art section describes electroplating defect/pinholes with Cu to visually mark the defect. This is extremely close to the invention.
U.S. Pat. No. 5,708,371 (Koyama) shows a method for using a photo-induced current in a conductive line having a defect or high resistance area. However, this reference differs from the invention.
U.S. Pat. No. 4,431,967 (Nishioka) shows a method for observing electrical defects with a LCD film/plate.
U.S. Pat. No. 4,980,019 (Baerg et al.) teaches an etch back process for semiconductor failure analysis.
U.S. Pat. No. 4,019,129 (Gra) shows a method for measuring defects in insulating films by plating and measuring the electric current of the plating.
A principle objective of the invention is to locate defective contacts or vias during semiconductor processing.
It is another objective of the invention to facilitate chip analysis by rapidly locating defective contacts or vias in a semiconductor device.
It is another objective of the invention to evaluate the degree of resistivity of contacts or vias in a semiconductor device.
It is another objective of the invention to form a cap over defective contacts or vias in a semiconductor surface whereby this cap serves as a protecting layer over the contact or via area after defect analysis has been completed.
It is another objective of the invention to locate and analyze defective contacts or vias in a semiconductor surface by using an Optical Microscope.
It is another objective of the invention to provide a clear view of defective contacts or vias after Focused Ion Beam (FIB) milling of the identified defective contacts or vias.
In accordance with the objectives of the invention a new method is provided to locate defective contacts or vias in a semiconductor surface of a wafer. A battery like arrangement of cathode-anode is constructed whereby the wafer under test, connected to a conducting wire, forms the cathode terminal and a copper plate, also connected to a conducting wire, forms the anode terminal. The surface area of the wafer under test wherein defective contacts or vias need to be identified and the copper plate are immersed in a CuSO4xe2x80x94H2O solution. A positive dc voltage is applied to the copper plate (the anode), dc current flows from the anode (the copper plate) to the cathode (the wafer under test). The dc current ionizes the CuSO4 solution and forms Cu2+ ions. These Cu2+ ions will, due to the dc voltage difference between the anode and the cathode plate, diffuse to the immersed surface of the wafer under test and will accumulate on this surface where such accumulation is most likely. Concentrations of Cu2+ ions will accumulate around areas of low resistance on the semiconductor surface, since low resistance results in high current density. Areas of low resistance are areas of defective contacts and vias in the surface of a wafer. Normal (not defective) contacts and vias provide a good surface for nucleation during electroplating. Areas of low resistance (defective contacts or vias) will, by contrast, result in the deposition of Cu2+ ions around these defective contacts and vias. The concentrations of Cu2+ ions will remain in place after the wafer under test is removed from the immersion bath, analyses of the defective contacts and vias in the semiconductor surface can now proceed quickly and effectively since the accumulated copper on the surface under test provides a clear indication as to the presence of defective contacts and vias in the semiconductor surface.
These defective contacts and vias may be missing via plugs, poor metal deposition in the contact opening, poor planarization of the contacts, potential for electromigration in the contact plug, poor contact profile, contact under-etch or over-etch.